Active phase shift compensation network



y 9, 1967 R. T. MATSUMOTO 3,319,079

ACTIVE PHASE SHIFT COMPENSATION NETWORK I Filed April 2, 1964 2 Sheets-Sheet l MAGNETIC READ HEAD FIG. 2

INVENTOR. RAYMOND T. MATSUMOTO ATTORNEY May 1967 R. T. MATSUMOTO 3,319,079

ACTIVE PHASE SHIFT COMPENSATION NETWORK I Filed April 2, 1964 2 Sheets-Sheet 2 vag- I l I I Zl I RI l I I I I :Z (INPUT) I I I I I I I I -l I I I I I LOAD I r -j I I I, I I T a" I I 24 I CONSTANT I CURRENT LSOURCE FIG. 3

INVENTOR.

RAYMOND T. MATSUMOTO ATTORNEY United States Patent 3,319,079 ACTIVE PHASE SHIFT COMPENSATION NETWORK Raymond T. Matsumoto, Cypress, Califi, assignor to I North American Aviation, Inc. Filed Apr. 2, 1964, Ser. No. 356,863 1 Claim. (Cl. 30788.5)

This invention relates to an active compensation network, and more particularly to an active two-port network for phase shift compensation.

In many circuits, it is often desirable to provide compensation networks in order to realize desired gain and phase shift or stability characteristics. If an active network is connected in series with a passive network for that purpose, the gain of the active element is not decreased as frequency increases and the passive network generally decreases the overall circuit gain without increasing the bandwidth of the active element.

An object of this invention is to provide an active compensation network with the gain of the active element decreasing as frequency is increased.

Another object is to provide an active compensation network in which the phase shift characteristics of the active element need not be considered. A related object is to provide a network which may readily be employed to selectively introduce poies and zeros in the s plane to reshape the response of a circuit.

These and other objects of the invention are achieved by incorporating phase shift networks around a transistor, thereby requiring less gain from the transistor as frequency is increased. The phase shift networks comprise a shunt impedance connected to the base of the transistor, and a series impedance connected to the emitter of the transistor.

Other objects and advantages of the invention will become apparent from the following detailed description with reference to the drawings in which:

FIG. 1 is a circuit diagram of an active two-port network in accordance with the invention;

FIG. 2 is a diagram of a circuit illustrating one advantageous application of the invention; and

FIG. 3 is a diagram of a circuit illustrating another advantageous application of the invention.

The invention illustrated in FIG. 1 comprises a transistor T and two impedance networks Z and Z The network Z is connected in shunt to the input terminal to which the base of the transistor is connected, and the network Z is connected in series between an output terminal 11 and the emitter of the transistor. In practice, the output terminal 11 may be connected to a source of potential, or ground, and the output taken from the collector of the transistor T In either case it is preferred to drive a low impedance load, such as the emitter of a grounded base transistor or the base of a grounded emitter stage having a large voltage gain.

Each impedance network includes a resistor in parallel with a capacitor. In the shunt impedance Z a resistor R and a capacitor C provide a negative phase shift at frequencies determined primarily by the product R C while in the series impedance Z a resistor R and a capacitor C provide a positive phase shift at frequencies determined primarily by the product R C If R C is greater than R C a negative phase shift is produced by the circuit at low frequencies; but as frequency increases, a positive phase shift is produced. Accordingly, if R C is greater than R C a lag-lead compensation network is provided. Similarly, if R C is greater than R C a leadlag compensation network is provided.

,The current gain of the circuit at low frequencies is determined primarily by the ratio R /R of the resistors.

At higher frequencies, the gain is determined primarily 3,319,979 Patented May 9, 1967 by the ratio C /C of the capacitors. If the capacitors are equal, the gain at high frequencies is equal to unity.

As frequency increases the current gain required of the transistor decreases if R 0 R2 C and its bandwidth (the frequency at which the transistor introduces phase shift) is increased. It will be noted with reference to FIG. 3 that the bandwidth of the transistor T need not be considered in the design of a feedback loop if the cutoff frequency of the other transistors is within that band width.

The impedance network Z should be designed to provide an impedance which decreases with frequency increase so that the transfer of energy from a current source at the input terminal 10 to the transistor base decreases in order that the design of the impedance network Z be easier to design for a given application. However, that is not essential. The impedance network Z is then designed to compensate for the phase shift introduced by Z Its magnitude may decrease with frequency, but it should be greater than, or equal to, the magnitude of the impedance network Z at higher frequencies in order to attenuate the current gain.

Although all design considerations which may be encountered in different applications could not be expected to fall within one general rule, or set of general rules, it is believed that the foregoing considerations will enable one skilled in the art to use the circuit of FIG. 1 to advantage by using standard design techniques, such as judicially locating the poles and zeros in the .3 plane.

A particular advantage of this invention is that in any application, the pole-zero location of the circuit in which it is employed for compensation may be very well controlled. Some of its other important characteristics are that at low frequencies current gain depends on the value of the resistors R and R and there is negligible phase shift in the current gain, while at high frequencies the current gain depends upon the value of the capacitors C and C and phase shift may be made negligible for frequencies within the pass band of the overall circuit.

As noted hereinbefore, if the time constant of the in1- pedance network Z is greater than that of the impedance network Z the overall circuit provides lag-lead compensation; if the opposite is true, the circuit provides leadlag compensation. It differs from a passive lag-lead or lead-lag network because it introduces gain. The gain is determined by the ratio R /R within the pass-band of the circuit. It also differs from the combination of a transistor in series with a passive compensating network in that it decreases the gain of the transistor T The pole-zero location introduced by the circuit (as determined by the impedance networks Z and Z is preferably placed at a frequency lower than the bandwidth of the transistor T for lag-lead compensation so that the phase shift of the transistor T need not be considered in the overall transfer function for frequencies less than that frequency F which is proportional to C times the upper bandwidth frequency of the transistor divided by C Thus with a judicious choice of capacitors C and C a lag-lead compensation circuit is readily provided with attenuation at high frequencies and no phase shift at frequencies below the frequency F. It is also possible to provide a lead-lag network in a similar manner'with only some loss of overall bandwidth.

As noted hereinbefore, a major advantage of the invention is that it may be used to introduce a pole and a zero to reshape the response of a circuit. FIG. 2 illustrates that advantage in a practical application.

In a magnetic disc, drum or tape memory system, the output voltage signal is dependent upon the load. In some instances, it is desirable to have as a load a low nput impedance amplifier, but such a low impedance load iistorts the output signal because of the high L/R time :onstant introduced by the low input impedance conlected to the relatively high inductance of the read head. For instance, if the input impedance is assumed to be R is shown in FIG. 2, the voltage appearing at the base of in amplifier transistor T is:

Because of the high L/R time constant, the network response will be distorted. To compensate for that distortion of the signal at the base of the transistor T the compensation circuit of FIG. 1 is provided Where Z is employed to cancel the pole R /L of Equation 1, and Z is employed to introduce a new pole at a higher frequency. The voltage signal at the output terminal 11' connected to the collector of the transistor T is the same as if the input impedance of the amplifier T were higher than R In that manner a read amplifier without distortion due to a low input impedance may be readily provided. As noted hereinbefore, the output may be taken from either the emitter or the collector of the transistor T In either case, it is preferable to drive a low impedance load such as the base of a grounded emitter stage with a large voltage gain.

FIG. 3 is a special buffer amplifier circuit illustrating the advantageous application of the invention in a feedback amplifier. Most amplifiers are built with a passive series feedback network. If an active element is provided in the feedback loop, it is connected in series with the passive network. In the circuit of FIG. 3, the feedback network decreases the gain of the active element T and introduces negligible phase shift at high frequencies below F, the frequency defined hereinbefore with reference to FIG. 1. Also, by decreasing the, gain of the active element T a wider band of frequencies for which the active element introduces negligible phase shift is achieved by a simple design.

The characteristics of this special amplifier include high input impedance greater than 4 megohms at low frequencies, made possible by amplifying the current of an input transistor T by transistors T and T and coupling that current through transistor T to transistor T The bandwidth of the overall feedback amplifier circuit may be readily designed with a bandwidth greater than 500 kc. for small signals and gain may also be readily adjusted with a minimum of design effort. The feedback network for stabilization, which includes the compensation network of FIG. 1 and resistors 20 and 21, allows the transistors T and T to introduce phase shifts at frequencies which will not affect stability. The compensation network is especially important in that regard in that it introduces gain at low frequencies and no gain or phase shift at high frequencies.

The transistors T and T are preferably matched to enable the difference between the input and output signals to be adjusted to zero. If a low-impedance signal source is provided, the amplifier is capable of translating a signal change from 10 volts to +10 volts within three microseconds with a maximum current input at the base of the transistor T 3 of 10 microamperes direct current. The components of a typical design are as follows:

T 2N709 T T 2N206O T 2N 1 6 1 3 R 22K R 2.2K C -pf- 6 8 C -pf- 6 8 Resistor 20 22K Resistor 21 3 3 K Resistor 22 17K 4 Resistor 23 3.3K Resistor 24 3.9K Resistor 25 20K Resistor 26 13K Load 27 8K Diodes D to D 1N9l6 Zener diodes D D7 1N753 +V1 24 V v ()24 A tolerance of :10% is preferred for the power supplies and i5% for all resistors. Diodes D to D are provided to protect the base emitter junctions of the transistors T T T and T The diodes D and D bias the transistor T to provide a constant current and the diode D is provided to limit the collector to emitter voltage of the transistor T It also keeps the emitter of the transistor T at a constant potential with respect to the potential +V The high impedance buffer amplifier provides negligible difference between input and output signals with a wide bandwidth, large signal response. These two characteristics are difficult to achieve, but were here easily achieved with the stabilizing network of FIG. 1.

The transfer function T(s) of that stabilizing lag-lead network, which is the ratio of I to 1 is given by where I =input current to the base of the transistor T I =output current to the base of the transistor T assuming it is connected to ground B =low frequency current gain of the transistor T w =gain-bandwidth product in radians S=complex frequency variable 'i' ok and the low frequency gain is:

2 1 1 01. while the high frequency gain is:

Q B 02 1 ri- 0 1 t z 'z -iand the low frequency value of the right-hand side of that expression is k, then if C kC the right-hand side of that expression increases in magnitude with frequency to the maximum value of C /C but if C kC the right-hand side of that expression decreases to the value C /C as frequency increases. When C =kC the right-hand side of that expression remains at the value k for all frequencies and the transfer function defined by Equation 2 becomes independent of C and C If C is greater than kC a phase lag and then a phase lead occurs as frequency is increased.

If the frequency of the signal being translated is high enough so that the Equation 7 approaches C /C the transfer function defined by Equation 4 is accurate for either lag-lead or lead-lag compensation as long as Thus, within the pass-band of the transistor T a very stable, well-controlled pole-zero configuration with gain may be realized in an active compensation network with a transistor having a large gain-bandwidth product.

It is to be understood that the applications of the in vention described with reference to FIGS. 2 and 3 are only illustrative. Numerous other applications may be devised by those skilled in the art. The appended claim is therefore intended to cover the invention in its broadest aspects without regard to specific applications, environments or operating requirements.

What is claimed is:

An active, two-port compensation network having a transfer function T(s), comprising:

a transistor having a base, emitter and collector, and

having a low frequency current gain B a shunt impedance Z connected to the base of said transistor consisting of a resistor R in parallel with a capacitor C a series impedance Z connected to the emitter of said transistor consisting of a resistor R in parallel wit] a capacitor C in which References Cited by the Examiner UNITED STATES PATENTS 2,885,495 5/1959 Sziklai et al 33021 X 2,914,682 11/1959 Taylor 307-885 2,996,683 8/1961 Lefkowitz 330-21 3,148,285 9/1964 Tedeschi et al. 30788.5 3,205,455 9/1965 Gunn et a1 33218 3,210,681 10/1965 Rhodes 33021 X ARTHUR GAUSS, Primary Examiner.

J. JORDAN, Assistant Examiner. 

